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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 103 db, 192 khz 8-channel d/a converter features ! advanced multi-bit delta sigma architecture ! 24-bit conversion ! automatic detection of sample rates up to 192 khz ! 103 db dynamic range ! -88 db thd+n ! single-ended output architecture ! direct stream digital mode ? non-decimating volume control ? on-chip 50 khz filter ? matched pcm and dsd analog output levels ! compatible with industry-standard time division multiplexed (t dm) serial interface ! selectable digital filters ! volume control with 1/2-db step size and soft ramp ! low clock jitter sensitivity ! +5 v analog supply, +2.5 v digital supply ! separate 1.8 to 5 v logic supplies for the control & serial ports description the cs4384 is a complete 8- channel digital-to-analog system. this d/a system includes digital de-emphasis, half-db step size volume control, atapi channel mix- ing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma mod- ulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. follow- ing this stage is a multi- element switched capacitor stage and low-pass filter with single-ended analog outputs. the cs4384 also has a proprietary dsd processor which allows for vo lume control and 50 khz on-chip fil- tering without an intermediate decimation stage. it also offers an optional path for direct dsd conversion by di- rectly using the multi-element switched capacitor array. the cs4384 accepts pcm data at sample rates from 4 khz to 216 khz, dsd audio data, and delivers excel- lent sound quality. these features are ideal for multi- channel audio systems including sacd players, a/v re- ceivers, digital tv?s, mixing consoles, effects processors, sound cards and automotive audio systems. this product is available in 48-pin lqfp package and is available in both automotive (-40 c - +85 c) and commercial (-10 c - +70 c) temperature grades. for full ordering information see page 50 . control port supply = 1.8 v to 5 v register/hardware configuration internal voltage reference reset serial interface level translator level translator tdm serial audio input digital supply = 2.5 v hardware mode or i 2 c/spi software mode control data analog supply = 5 v eight channels of single-ended outputs 8 pcm serial audio input volume controls digital filters switch-cap dac and analog filters multi-bit ? modulators dsd audio input dsd processor -volume control -50 khz filter external mute control mute signals 2 8 serial audio port supply = 1.8 v to 5 v august '05 ds620a1 cs4384
2 ds620a1 cs4384 table of contents 1. pin description............................................................................................................. .................... 6 2. characteristics and specificat ions........... ................. ................ ................ ................ .......... 8 specified operating conditions ................................................................................................. ... 8 absolute maximum ratings....................................................................................................... ........ 8 dac analog characteristics..................................................................................................... ...... 9 dac analog characteristics - all modes (continued) ........................................................ 10 power and thermal characteristics........................................................................................ 10 combined interpolation & on-chip analog fi lter response............ ............. ............. ...... 11 combined interpolation & on-chip analog fi lter response............ ............. ............. ...... 12 dsd combined digital & on-chi p analog filter response ..... ................. ................ ............ 12 digital characteristics ........................................................................................................ .......... 13 switching characteristics - pcm ................................................................................................ 14 switching characteristics - dsd................................................................................................ .15 switching characteristics - control port - i2 c format.................................................... 16 switching characteristics - control port - spi? format ............................................... 17 3. applications ................................................................................................................ ................... 20 3.1 master clock............................................................................................................... ................... 20 3.2 mode select............................................................................................................... ................... 21 3.3 digital interface formats .................................................................................................. ............. 22 3.3.1 olm #1 ................................................................................................................... ............. 23 3.3.2 olm #2 ................................................................................................................... ............. 23 3.3.3 olm #3 ................................................................................................................... ............. 24 3.3.4 olm #4 ................................................................................................................... ............. 24 3.3.5 tdm ...................................................................................................................... ............... 25 3.4 oversampling modes......................................................................................................... ............ 25 3.5 interpolation filter ....................................................................................................... ................... 25 3.6 de-emphasis ................................................................................................................ ................. 26 3.7 atapi specification ........................................................................................................ ............... 26 3.8 direct stream digital (dsd) mode........................................................................................... ...... 27 3.9 grounding and power supply arrangements .......... ...................................................................... 28 3.9.1 capacitor placement...................................................................................................... ...... 28 3.10 analog output and filtering ............................................................................................... .......... 28 3.11 the mutec outputs ......................................................................................................... .......... 29 3.12 recommended power-up sequence .................... ...................................................................... 29 3.12.1 hardware mode........................................................................................................... ....... 29 3.12.2 software mode ........................................................................................................... ........ 30 3.13 recommended proced ure for switching operational modes...................................................... 30 3.14 control port interface ........................... ......................................................................... .............. 30 3.14.1 map auto increment ....... ............................................................................................... .... 30 3.14.2 i2c mode ................................................................................................................ ............ 30 3.14.3 spi? mode............................................................................................................... ......... 32 3.15 memory address pointer (map) ................. ............................................................................ .... 32 3.15.1 incr (auto map increment enable) ........ .......................................................................... 32 3.15.2 map4-0 (memory address pointer) ................................................................................... 32 4. register quick reference ................................................................................................... .... 33 5. register description ........................................................................................................ .......... 34 5.1 chip revision (address 01h) ................................................................................................ ......... 34 5.1.1 part number id (part) [read only]....................................................................................... 3 4 5.2 mode control 1 (address 02h) ............................................................................................... ........ 34 5.2.1 control port enable (cpen) ...................... ......................................................................... .34 5.2.2 freeze controls (freeze) ................................................................................................. .35 5.2.3 pcm/dsd selection (dsd/pcm)......................................................................................... 35
ds620a1 3 cs4384 5.2.4 dac pair disable (dacx_dis) ............................................................................................ 35 5.2.5 power down (pdn)......................................................................................................... ..... 35 5.3 pcm control (address 03h) .................................................................................................. ......... 35 5.3.1 digital interface format (dif)........................................................................................... .... 35 5.3.2 functional mode (fm) ..................................................................................................... ..... 36 5.4 dsd control (address 04h) .................................................................................................. ......... 36 5.4.1 dsd mode digital interface format (dsd_dif) .................................................................. 36 5.4.2 direct dsd conversion (dir_dsd)..................................................................................... 37 5.4.3 static dsd detect (static_dsd) ...................................................................................... 37 5.4.4 invalid dsd detect (invalid_dsd).................................................................................... 37 5.4.5 dsd phase modulation mode select (dsd _pm_mode).................................................... 37 5.4.6 dsd phase modulation mode enable (dsd_p m_en) ........................................................ 38 5.5 filter control (address 05h) ............................................................................................... ............ 38 5.5.1 interpolation filter select (filt_sel)..... ............................................................................. 3 8 5.6 invert control (address 06h) ............................................................................................... ........... 38 5.6.1 invert signal polarity (inv_xx) .......................................................................................... ... 38 5.7 group control (address 07h) ................................................................................................ ......... 38 5.7.1 mutec pin control (mutec) ................................................................................................ 38 5.7.2 channel a volume = channel b volume (p x_a=b)............................................................. 39 5.7.3 single volume co ntrol (snglvol) ..................................................................................... 39 5.8 ramp and mute (address 08h) ................................................................................................ ...... 39 5.8.1 soft ramp and zero cross control (szc) ........................................................................... 39 5.8.2 soft volume ramp-up afte r error (rmp_up) ..................................................................... 40 5.8.3 soft ramp-down before filter mode ch ange (rmp_dn) ................................................... 40 5.8.4 pcm auto-mute (pamute) .... ............................................................................................. 40 5.8.5 dsd auto-mute (damute) ................................................................................................. 40 5.8.6 mute polarity and detect (mutep1:0)..... ...................................................................... 41 5.9 mute control (address 09h) ........................ ......................................................................... .......... 41 5.9.1 mute (mute_xx) ........................................................................................................... ....... 41 5.10 mixing control (address 0ah, 0dh, 10h, 13h).............................................................................. 4 1 5.10.1 de-emphasis control (px_ dem1:0).................................................................................. 41 5.11 atapi channel mixing and muting (atapi) ... ............................................................................. 42 5.12 volume control (add ress 0bh, 0ch, 0eh, 0fh, 11h, 12h, 14h, 15h) ........................................... 43 5.12.1 digital volume control (x x_vol7:0) .................................................................................. 43 5.13 pcm clock mode (address 16h)..................... ......................................................................... .... 43 5.13.1 master clock divide by 2 enable (mclkdi v).................................................................... 43 6. filter response plots ......... ................ ................. ................ ................ ................ ............ ......... 44 7. references.................................................................................................................. .................... 48 8. parameter definitions....................................................................................................... ......... 48 9. package dimensions .......................................................................................................... .......... 49 10. ordering information ....................................................................................................... ....... 50 11. revision history .......................................................................................................... ............... 50
4 ds620a1 cs4384 list of figures figure 1. serial audio interface timing........................................................................................ .............. 14 figure 2. tdm serial audio interface timing .................................................................................... ......... 14 figure 3. direct stream digital - serial audio input timing.................................................................... .... 15 figure 4. direct stream digital - serial audio input timing for phase modulation mode........................... 15 figure 5. control port timing - i2c format....... .............................................................................. ............ 16 figure 6. control port timing - spi format......... ............................................................................ ........... 17 figure 7. typical connection diagram, software mo de............................................................................ .18 figure 8. typical connection diagr am, hardware mode ........................................................................... 1 9 figure 9. format 0 - left-justified up to 24-bit data .......................................................................... ........ 22 figure 10. format 1 - i2s up to 24-bit data ...... .............................................................................. ............ 22 figure 11. format 2 - right-justified 16-bit da ta .............................................................................. ......... 22 figure 12. format 3 - right-justified 24-bit da ta .............................................................................. ......... 22 figure 13. format 4 - right-justified 20-bit da ta .............................................................................. ......... 22 figure 14. format 5 - right-justified 18-bit da ta .............................................................................. ......... 23 figure 15. format 8 - one line mode 1........... ............................................................................... ........... 23 figure 16. format 9 - one line mode 2........... ............................................................................... ........... 23 figure 17. format 10 - one line mode 3......................................................................................... .......... 24 figure 18. format 11 - one line mode 4......................................................................................... .......... 24 figure 19. format 12 - tdm mode................................................................................................ ............. 25 figure 20. de-emphasis curve................................................................................................... ............... 26 figure 21. atapi block diagram (x = channel pair 1, 2, 3, or 4) ............................................................... 2 6 figure 22. dsd phase modulation mode diagram ................................................................................... .27 figure 23. full-scale output ................................................................................................... ................... 28 figure 24. recommended output filter........................................................................................... .......... 28 figure 25. recommended mute circuitry .......................................................................................... ........ 29 figure 26. control port timing, i2c mode ....................................................................................... ........... 31 figure 27. control port timing, spi mode ....................................................................................... .......... 32 figure 28. single-speed (fast) stopband rejection.............................................................................. ..... 44 figure 29. single-speed (fast) transition band .. ............................................................................... ........ 44 figure 30. single-speed (fast) transition band (d etail) ........................................................................ ..... 44 figure 31. single-speed (fast) passband ripple ................................................................................. ...... 44 figure 32. single-speed (slow) stopband rejection .............................................................................. ... 44 figure 33. single-speed (slow) transition band................................................................................. ....... 44 figure 34. single-speed (slow) tr ansition band (detail)........................................................................ .... 45 figure 35. single-speed (slow) passband ripple................................................................................. ..... 45 figure 36. double-speed (fast) stopband rejection .............................................................................. ... 45 figure 37. double-speed (fast) transition band..... ............................................................................ ....... 45 figure 38. double-speed (fast) tr ansition band (detail)........................................................................ .... 45 figure 39. double-speed (fast) passband ripple................................................................................. ..... 45 figure 40. double-speed (slow) st opband rejection .............................................................................. .. 46 figure 41. double-speed (slow) transition band ................................................................................. ..... 46 figure 42. double-speed (slow) transition band (detail) ........................................................................ .. 46 figure 43. double-speed (slow) passband ripple ................................................................................. ... 46 figure 44. quad-speed (fast) st opband rejection ................................................................................ .... 46 figure 45. quad-speed (fast) transition band ....... ............................................................................ ....... 46 figure 46. quad-speed (fast) tr ansition band (detail) .......................................................................... .... 47 figure 47. quad-speed (fast) passband ripple ........ ........................................................................... ..... 47 figure 48. quad-speed (slow) st opband rejection................................................................................ ... 47 figure 49. quad-speed (slow) transition band.. ................................................................................. ...... 47 figure 50. quad-speed (slow) tran sition band (detail).......................................................................... ... 47 figure 51. quad-speed (slow) passband ripple....... ............................................................................ .... 47
ds620a1 5 cs4384 list of tables table 1. single-speed mode standa rd frequencies ................................................................................ 20 table 2. double-speed mode standard frequencies............................................................................... 20 table 3. quad-speed mode standard frequencies ................................................................................. 20 table 4. pcm digital interface format, hardware mode options............................................................. 21 table 5. mode selection, hardware mode options ................................................................................. . 21 table 6. direct stream digital (dsd ), hardware mode options ................ ............................................... 21 table 7. digital interface formats - pcm mode...... ............................................................................ ...... 36 table 8. digital interface format s - dsd mode .................................................................................. ...... 37 table 9. atapi decode .......................................................................................................... .................. 42 table 10. example digital volume settings ........ .............................................................................. ........ 43
6 ds620a1 cs4384 1. pin description pin name # pin description vd 4 digital power ( input ) - positive power supply for the digital section. gnd 5 31 ground ( input ) - ground reference. should be connected to analog ground. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. table 1 illustrates several standard audio sample rates and the required master clock frequency. lrck 7 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sdin1 sdin2 sdin3 sdin4 8 11 13 14 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 9 serial clock ( input ) - serial clock for the serial audio interface. vlc 18 control port power ( input ) - determines the required signal level for the control port. rst 19 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. filt+ 20 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. requires the capacitive decoupling to analog ground, as shown in the typical connection diagram. vq 21 quiescent voltage ( output ) - filter connection for internal quiescent voltage. mutec1 mutec234 41 22 mute control ( output ) - these pins are intended to be used as a control for external mute circuits to prevent the clicks and pop s that can occur in any single supply system. aout1 aout2 aout3 aout4 aout5 aout6 aout7 aout8 39 38 35 34 29 28 25 24 analog output ( output ) - the full scale analog output level is specified in the analog characteristics specification table. sdin3 gnd tst_out aout5 tst_out aout4 va tst_out aout6 tst_out aout7 6 2 4 8 10 1 3 5 7 9 11 1 2 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mclk dsd2 vd sdin1 m4(tst) dsd3 dsd1 gnd sclk sdin2 m3(tst) lrck dsd_sclk dsd6 dsd5 dsd7 cs4384 dsd8 vls sdin4 m2(scl/cclk) m1(sda/cdin) vlc rst filt+ vq mutec2 tst_out aout8 m0(ad0/cs) aout3 tst_out aout2 tst_out tst_out aout1 dsd4 mutec1
ds620a1 7 cs4384 va 32 analog power ( input ) - positive power supply for the analog section. refer to the recommended operating conditions for appropriate voltages. vls 43 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operating conditions for appropriate voltages. tst_out 23, 26 27, 30 33, 36 37, 40 test output - these pins need to floating and not connected to any trace or plane. software mode definitions scl/cclk 15 serial contro l port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i2c mode as shown in the typical connection diagram. sda/cdin 16 serial control data ( input/output ) - sda is a data i/o line in i2c mode and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram. cdin is the input data line for the control port interface in spi mode. ad0/cs 17 address bit 0 (i2c) / contro l port chip select (spi) ( input ) - ad0 is a chip address pin in i2c mode; cs is the chip select signal for spi format. tst 10 12 test - these pins need to be tied to analog ground. stand-alone definitions m0 m1 m2 m3 m4 17 16 15 12 10 mode selection ( input ) - determines the operational mode of the device as detailed in tables 4 and 5 . dsd definitions dsd_sclk 42 dsd serial clock ( input ) - serial clock for the direct stream digital audio interface. dsd1 dsd2 dsd3 dsd4 dsd5 dsd6 dsd7 dsd8 3 2 1 48 47 46 45 44 direct stream digital input ( input ) - input for direct stream digital serial audio data. pin name # pin description
8 ds620a1 cs4384 2. characteristics and specifications all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specifications are deri ved from measurements taken at nominal supply voltage and t a = 25 c. specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.25 v v v v specified temperature range -cqz -dqz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 3.2 6.0 6.0 v v v v input current any pin except supplies i in -10ma digital input voltage serial data port interface control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t op -55 125 c storage temperature t stg -65 150 c
ds620a1 9 cs4384 dac analog characteristics full-scale output sine wave, 997 hz (note 1) ; fs = 48/96/192 khz; test load r l = 3 k ? , c l = 100 pf ; measure- ment bandwidth 10 hz to 20 khz, unless otherwise specified. notes: 1. one-half lsb of triangular pdf dither is added to data. 2. performance limited by 16-bit quantization noise. parameters symbol min typ max unit cs4384-cqz dynamic performance - all pcm modes and dsd specified temperature range t a -10 - 70 c dynamic range 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 97 94 - - 103 100 97 94 - - - - db db db db total harmonic distortion + noise 24-bit -0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -88 -80 -40 -88 -74 -34 -82 -74 -34 - - - db db db db db db idle channel noise / signal-to-noise ratio - 100 - db cs4384-dqz dynamic performance - all pcm modes and dsd specified temperature range t a -40 - 105 c dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 94 91 - - 103 100 97 94 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -88 -80 -40 -88 -74 -34 -79 -71 -31 - - - db db db db db db idle channel noise / signal-to-noise ratio - 100 - db
10 ds620a1 cs4384 dac analog characteristics - all modes (continued) power and therma l characteristics notes: 3. v fs is tested under load r l and includes attenuation due to z out 4. current consumption increases with increasing fs within a given speed mode and is signal dependant. max values are based on highest fs and highest mclk. 5. i lc measured with no external loading on the sda pin. 6. power down mode is defined as rst pin = low with all clock and data lines held static. 7. valid with the recommended capacitor values on filt+ and vq as shown in figures 7 and 8 . parameters symbol min typ max units interchannel isolation (1 khz) - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output full scale differential- pcm, dsd processor output voltage direct dsd mode v fs 66%?v a 47%?v a 67%?v a 48%?v a 68%?v a 49%?v a vpp vpp output impedance (note 3) z out -130 - ? max dc current draw from an aout pin i outmax -1.0 -ma min ac-load resistance r l -3 -k ? max load capacitance c l -100 -pf quiescent voltage v q - 50% v a -vdc max current draw from v q i qmax -10 - a parameters symbol min typ max units power supplies power supply current normal operation, va= 5 v (note 4) vd= 2.5 v (note 5) interface current, vlc=5 v vls=5 v (note 6) power-down state (all supplies) i a i d i lc i ls i pd - - - - - 83 18 2 84 200 92 24 - - - ma ma a a a power dissipation (note 4) va = 5v, vd = 2.5v normal operation (note 6) power-down - - 460 1 540 - mw mw package thermal resistance ja jc - - 48 15 - - c/watt c/watt power supply rejection ratio (note 7) (1 khz) (60 hz) psrr - - 60 40 - - db db
ds620a1 11 cs4384 combined interpolation & on-c hip analog filter response the filter characteristics have been normalized to the samp le rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs. (see (note 12) ) notes: 8. slow roll-off interpolation filter is only available in software mode. 9. response is clock dependent and will scale with fs. 10. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement band width is from stopband to 1.34 fs. 11. de-emphasis is available only in single-speed mo de; only 44.1 khz de-emphasis is available in hardware mode. 12. amplitude vs. frequency plots of this data are available in the ?filter response plots? on page 44 . parameter fast roll-off unit min typ max combined digital and on-chip analog filt er response - single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 10) 102 - - db group delay - 10.4/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.36 0.21 0.14 db db db combined digital and on-chip analog filter response - double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 80 - - db group delay - 6.15/fs - s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .635 - - fs stopband attenuation (note 10) 90 - - db group delay - 7.1/fs - s
12 ds620a1 cs4384 combined interpolat ion & on-chip analog filter response (contined) dsd combined digital & on- chip analog filter response parameter slow roll-off (note 8) unit min typ max single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 64 - - db group delay - 7.8/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.36 0.21 0.14 db db db double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .792 - - fs stopband attenuation (note 10) 70 - - db group delay - 5.4/fs - s quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .868 - - fs stopband attenuation (note 10) 75 - - db group delay - 6.6/fs - s parameter min typ max unit dsd processor mode passband (note 9) to -3 db corner 0 - 50 khz frequency response 10 hz to 20 khz -0.05 - +0.05 db roll-off 27 - - db/oct direct dsd mode passband (note 9) to -0.1 db corner to -3 db corner 0 0 - - 26.9 176.4 khz khz frequency response 10 hz to 20 khz -0.1 - 0 db
ds620a1 13 cs4384 digital characteristics 13. any pin except supplies. transient currents of up to 100 ma on the input pins will not cause scr latch-up parameters symbol min typ max units input leakage current (note 13) i in --10 a input capacitance - 8 - pf high-level input voltage serial i/o control i/o v ih v ih 70% 70% - - - - v ls v lc low-level input voltage serial i/o control i/o v il v il - - - - 30% 30% v ls v lc high-level output voltage (i oh = -1.2 ma) control i/o v oh 80% - - v lc low-level output voltage (i ol = 1.2 ma) control i/o v ol --20%v lc mutec auto detect input high voltage v ih 70% - - va mutec auto detect input low voltage v il --30%va maximum mutec drive current i max -3-ma mutec high-level output voltage v oh -va-v mutec low-level output voltage v ol -0-v
14 ds620a1 cs4384 switching characteristics - pcm (inputs: logic 0 = gnd, logic 1 = vls, c l = 30 pf) notes: 14. after powering up, rst should be held low until after th e power supplies and clocks are settled. 15. see tables 1 - 3 for suggested mclk frequencies. 16. not required for tdm mode. parameters symbol min max units rst pin low pulse width (note 14) 1-ms mclk frequency 1.024 55.2 mhz mclk duty cycle (note 15) 45 55 % input sample rate - lrck (manual selection) single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 54 108 216 khz khz khz input sample rate - lrck (auto detect) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 54 108 216 khz khz khz lrck duty cycle (note 16) 45 55 % sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns lrck edge to sclk rising edge t lcks 5-ns sclk rising edge to lrck falling edge t lckd 5-ns sdin setup time before sclk rising edge t ds 3-ns sdin hold time after sclk rising edge t dh 5-ns sckh sckl t t sdin1 dh t ds t lcks t lckd t sclk lrck lcks t msb msb-1 sdinx t ds sclk lrck msb t dh t sckh t sckl t lcks msb-1 figure 1. serial audio interface timing figu re 2. tdm serial audio interface timing
ds620a1 15 cs4384 switching characteristics - dsd (logic 0 = agnd = dgnd; logic 1 = vls; c l =30pf) parameter symbol min typ max unit mclk duty cycle 40 - 60 % dsd_sclk pulse width low t sclkl 160 - - ns dsd_sclk pulse width high t sclkh 160 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns dsd clock to data transition (phase modulation mode) t dpm -20 - 20 ns sclkh t sclkl t dsdxx dsd_sclk sdlrs t sdh t figure 3. direct stream digital - serial audio input timing dpm t dsdxx dsd_sclk (64fs) dsd_sclk (128fs) dpm t figure 4. direct stream digital - serial audio input timing for phase modulation mode
16 ds620a1 cs4384 switching characteristics - control port - i2c format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 17. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 5. control port timing - i2c format
ds620a1 17 cs4384 switching characteristics - control port - spi ? format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 18. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 19. data must be held for sufficient time to bridge the transition time of cclk. 20. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 18) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 19) t dh 15 - ns rise time of cclk and cdin (note 20) t r2 -100ns fall time of cclk and cdin (note 20) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 6. control port timing - spi format
18 ds620a1 cs4384 vls mclk vd aout1 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ vq 7 6 lrck sclk sdin3 sdin2 39 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 sdin4 13 14 analog conditioning and muting aout2 38 analog conditioning and muting aout3 35 analog conditioning and muting aout4 34 analog conditioning and muting aout5 29 analog conditioning and muting aout6 28 analog conditioning and muting aout7 25 analog conditioning and muting aout8 24 analog conditioning and muting mutec1 41 22 mu t e dr iv e mutec2 34 11 31 gnd gnd 5 mic r o- controller vlc 0.1 f +1.8 v to +5 v 18 2 48 dsd4 3 42 dsd_sclk dsd1 dsd6 dsd5 dsd7 dsd2 dsd3 46 45 47 1 44 dsd8 16 15 scl/cclk sda/cdin ado/cs rst 19 17 2 k ? 2 k ? note: necessary for i 2 c control port operation not e* cs4384 tst* *pins: 10, 12 dsd audio source 220 ? 470 ? 470 ? digit al audio source pcm pins: 23, 26, 27, 30, 33, 36, 37, 40 tst_out figure 7. typical connection diagram, software mode
ds620a1 19 cs4384 vls cs4384 mclk vd 8 32 0.1 f + 1 f +2.5 v sdin1 9 7 6 lrck sclk sdin3 sdin2 va 0.1 f + 1 f +1.8 v to +5 v +5 v 4 43 sdin4 13 14 11 31 gnd gnd 5 stand-alone mode configuration vlc 0.1 f +1.8 v to +5 v 18 2 48 dsdb2 3 12 m3 dsda1 dsdb3 dsda3 dsda4 dsdb1 dsda2 46 45 47 1 44 dsdb4 16 15 m2 m1 m0 rst 19 17 42 dsd_sclk 10 m4 220 ? 470 ? digital audio source pcm dsd audio source 470 ? 0.1 f optional 47 k ? aout1 1 f 0.1 f + + 20 21 filt+ vq 39 0.1 f 47 f analog conditioning and muting aout2 38 analog conditioning and muting aout3 35 analog conditioning and muting aout4 34 analog conditioning and muting aout5 29 analog conditioning and muting aout6 28 analog conditioning and muting aout7 25 analog conditioning and muting aout8 24 analog conditioning and muting mutec1 41 22 mu t e dr iv e mutec2 3 4 pins: 23, 26, 27, 30, 33, 36, 37, 40 tst_out figure 8. typical connection diagram, hardware mode
20 ds620a1 cs4384 3. applications the cs4384 serially accepts twos co mplement formatted pcm data at standar d audio sample rates including 48, 44.1 and 32 khz in ssm, 96, 88.2 and 64 khz in dsm, and 192, 176.4 and 128 khz in qsm. audio data is input via the serial data input pins (sdinx). the left/right clo ck (lrck) determines which channel is currently being input on sdinx, and the serial clock (sclk) clocks audio data into the input data buffer. for more information on serial audio interfaces see an282 ?the 2-channe l serial audio interface: a tutorial?. the cs4384 can be configured in hardware mode by the m0, m1, m2, m3 and m4 pins and in software mode through i2c or spi. 3.1 master clock mclk/lrck must be an integer ratio as shown in tables 1 - 3 . the lrck frequency is equal to fs, the frequency at which words for each channel are input to the device. the mclk-to-lrck frequency ratio and speed mode is detected automatically during the init ialization sequence by counting the number of mclk transitions during a single lrck period and by detectin g the absolute speed of mclk. internal dividers are then set to generate the proper internal clocks. tables 1 - 3 illustrate several stan dard audio sample rates and the required mclk and lrck frequencies. please note there is no required phase relationship, but mclk, lrck and sclk must be synchronous. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 1. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. quad-speed mode standard frequencies = denotes clock ratio and sample rate combinations which are not supported under auto speed-mode detection. please see ?switching characteristics - pcm? on page 14 .
ds620a1 21 cs4384 3.2 mode select in hardware mode operation is determined by the mo de select pins. the state of these pins are continually scanned for any changes. these pins require co nnection to supply or ground as outlined in figure 8 . for m0, m1, m2 supply is vlc and for m3 and m4 supply is vls. tables 4 - 6 show the decode of these pins. in software mode, the operational mode and data format are set in the fm and dif registers. m1 (dif1) m0 (dif0) description format figure 00 left justified, up to 24-bit data 0 9 01 i 2 s, up to 24-bit data 1 10 10 right justified, 16-bit data 2 11 11 right justified, 24-bit data 3 12 table 4. pcm digital interface format, hardware mode options m4 m3 m2 (dem) m1 m0 description 00 0 table 4 single-speed without de-emphasis (4 khz to 50 khz sample rates) 00 1 single-speed with 44.1 khz de-emphasis; see figure 20 01 0 double-speed (50 khz to 100 khz sample rates) 01 1 quad-speed (100 khz to 200 khz sample rates) 10 0 auto speed-mode detect (32 khz to 200 khz sample rates) 10 1 auto speed-mode detect with 44.1 khz de-emphasis; see figure 20 11 table 6 dsd processor mode table 5. mode selection, hardware mode options m2 m1 m0 description 000 64x oversampled dsd data with a 4x mclk to dsd data rate 001 64x oversampled dsd data with a 6x mclk to dsd data rate 010 64x oversampled dsd data with a 8x mclk to dsd data rate 011 64x oversampled dsd data with a 12x mclk to dsd data rate 100 128x oversampled dsd data with a 2x mclk to dsd data rate 101 128x oversampled dsd data with a 3x mclk to dsd data rate 110 128x oversampled dsd data with a 4x mclk to dsd data rate 111 128x oversampled dsd data with a 6x mclk to dsd data rate table 6. direct stream digital (dsd), hardware mode options
22 ds620a1 cs4384 3.3 digital interface formats the serial port operates as a slave and supports the i2s, left-justified, right-justified, one-line mode (olm) and tdm digital interface formats with varying bit depths from 16 to 32 as shown in figures 9 - 19 . data is clocked into the dac on the rising edge. olm and tdm configurations are only supported in soft- ware mode. lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 9. format 0 - left-jus tified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb figure 10. format 1 - i2s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 11. format 2 - ri ght-justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 12. format 3 - ri ght-justified 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 13. format 4 - ri ght-justified 20-bit data
ds620a1 23 cs4384 3.3.1 olm #1 olm #1 serial audio interface form at operates in single, double, or quad-spe ed mode and will slave to sclk at 128 fs. six channels of msb first 20-bit pcm data are input on sdin1. the last two channels are input on sdin4. 3.3.2 olm #2 olm #2 serial audio interface form at operates in single, double, or quad-spe ed mode and will slave to sclk at 256 fs. six channels of msb firs t 24-bit pcm data are input on sdin1. the last two channels are input on sdin4. lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 14. format 5 - ri ght-justified 18-bit data lrck sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 20 clks 20 clks sdin4 sdin1 dac_a2 dac_a3 dac_a4 dac_b1 dac_b4 dac_b2 dac_b3 figure 15. format 8 - one line mode 1 lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 24 clks 24 clks 128 clks lrck sclk sdin1 sdin4 dac_a4 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 dac_b4 figure 16. format 9 - one line mode 2
24 ds620a1 cs4384 3.3.3 olm #3 olm #3 serial audio inte rface format o perates in single, do uble, or quad-speed mode and will slave to sclk at 256 fs. eight channels of msb first 20-bit pcm data are input on sdin1. 3.3.4 olm #4 olm #4 serial audio inte rface format o perates in single, do uble, or quad-speed mode and will slave to sclk at 256 fs. eight channels of msb first 24-bit pcm data are input on sdin1. lsb msb 20 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 128 clks lrck sclk sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 lsb msb 20 clks dac_a4 lsb msb 20 clks dac_b4 figure 17. format 10 - one line mode 3 lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 128 clks lrck sclk sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 lsb msb 24 clks dac_a4 lsb msb 24 clks dac_b4 figure 18. format 11 - one line mode 4
ds620a1 25 cs4384 3.3.5 tdm the tdm serial audio interface form at operates in single, double, or quad-speed mode and will slave to sclk at 256 fs. data is received mo st significant bit first on the firs t sclk after an lrck transition and is valid on the rising edge of sclk. lrck identifies the start of a new frame and is equal to the sample rate, fs. lrck is sampled as valid on the rising sclk edge preceding the most significant bit of the first data sample and must be held valid for one sclk peri od. each time slot is 32 bits wide, with the valid data sample left justified within the time slot wi th the remaining bits being zero padded. 3.4 oversampling modes the cs4384 operates in one of three oversampling modes based on the input sample rate. mode selection is determined by the m4, m3 and m2 pins in hardware mode or the fm bits in software mode. single-speed mode supports input sample rates up to 50 khz an d uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode sup- ports input sample rates up to 200 khz and uses an oversampling ratio of 32x. the auto-speed mode detect feature allows for the auto matic selection of speed mo de based off of the in- coming sample rate. this a llows the cs4384 to accept a wide range of sample rates with no external inter- vention necessary. the auto-speed mode detect feature is available in both hardware and software mode. 3.5 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the cs4384 incorporates selectable interpolation filters for each mode of operatio n. a ?fast? and a ?slow? ro ll-off filter is available in each of single, double, and quad-speed modes. these filters have been designed to accommodate a va- riety of musical tastes and styles. the filt_sel bi t is used to select which filter is used (see the ?parameter definitions? on page 48 for more details). when in hardware mode, only the ?f ast? roll-off filter is available. filter specifications can be found in section 2 , and filter response plots can be found in figures 28 to 51 . dac_b2 lrck sclk lsb msb lsb msb lsb msb lsb msb lsb msb sdin1 dac_a1 dac_a2 dac_b1 dac_a3 256 clks 32 clks 32 clks 32 clks 32 clks 32 clks lsb msb dac_b3 32 clks lsb msb dac_a4 32 clks lsb msb dac_b4 32 clks lsb lsb msb zero data figure 19. format 12 - tdm mode
26 ds620a1 cs4384 3.6 de-emphasis the cs4384 includes on-chip digital de-emphasis filters. the de-emphasis feature is included to accommo- date older audio recordi ngs that utilize pre-emphasis equalizat ion as a means of noise reduction. figure 20 shows the de-emphasis curv e. the frequency response of the de-emphasis cu rve will scale proportionally with changes in sample rate, fs if the input sample rate does not match the coefficient which has been se- lected. in software mode the required de-emphasis filter coe fficients for 32 khz, 44.1 khz, or 48 khz are selected via the de-emphasis control bits. in hardware mode only the 44.1 khz coefficient is available (enabled through the m2 pin). if the input sample rate is not 44.1 khz and de-emphasis has been selected then the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual fs over 44,100. 3.7 atapi specification the cs4384 implements the channel mixing functions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 9 on page 42 and figure 21 for additional informa- tion. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 20. de-emphasis curve ? a channel volume control aout ax aoutbx left chan nel audio d ata right chan nel audio d ata bchannel volume control mute mute sdinx figure 21. atapi block diagram (x = channel pair 1, 2, 3, or 4)
ds620a1 27 cs4384 3.8 direct stream digital (dsd) mode in software mode the dsd/pcm bits (reg. 02h) are used to configure the device for dsd mode. the dsd_dif bits (reg 04h) then control the expect ed dsd rate and mclk ratio. the dir_dsd bit (reg 04h) selects between two propriet ary methods for dsd to analog conversion. the first method uses a decimation free dsd processing technique which allows for features such as matched pcm level output, dsd volume control, and 50khz on chip filter. the second method sends the dsd data directly to the on- chip switched-capacitor filter for conversion (without the above mentioned features). the dsd_pm_en bit (reg. 04h) selects phase modulation (data plus data inverted) as the style of data input. in this mode the dsd_pm_mode bit selects whether a 128fs or 64x clock is used for phase modulated 64x data (see figure 22 ). use of phase modulation mode may not directly effect the performance of the cs4384, but may lower the sensitivity to board level ro uting of the dsd data signals. the cs4384 can detect errors in the dsd data whic h does not comply with the sacd specification. the static_dsd and invalid_dsd bits (reg. 04h) allow the cs4384 to alter the incoming invalid dsd data. depending on the error, the data may either be attenuated or replaced with a muted dsd signal (the mutec pins would be set according to the damute bit (reg. 08h)). more information for any of these register bits can be found in the ?parameter definitions? on page 48 . the dsd input structure and analog outputs are designed to handle a nominal 0 db-sacd (50% modulation index) at full rated performance. signals of +3 db-sacd may be ap plied for brief periods of time however, performance at these levels is not guaranteed. if sustained +3 db-sacd le vels are required, the digital volume control should be set to -3.0 db. this same vo lume control register affects pcm output levels. there is no need to change the vol- ume control setting between pcm and dsd in order to have the 0 db output levels match (both 0 dbfs and 0 db- sacd will output at -3 db in this case). figure 22. dsd phase modulation mode diagram bcka (128fs) bckd (64fs) dsd_sclk dsdax, dsdbx d1 d1 d1 d0 d2 d2 d0 dsd_sclk dsdax, dsdbx bcka (64fs) dsd_sclk dsd phase modulation mode dsd normal mode not used not used not used
28 ds620a1 cs4384 3.9 grounding and power supply arrangements as with any high resolution converter, the cs4384 requ ires careful attention to power supply and grounding arrangements if its potential performance is to be realized. the typical connect ion diagram shows the rec- ommended power arrangements, with va, vd, vlc, and vls connected to clean supplies. if the ground planes are split between digital ground and analog gro und, the gnd pins of the cs4384 should be connect- ed to the analog ground plane. all signals, especially clocks, should be kept away fr om the filt+ and vq pins in order to avoid unwanted coupling into the dac. 3.9.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low value ceramic ca- pacitor being the closest. to further minimize impeda nce, these capacitors should be located on the same layer as the dac. if desired, a ll supply pins with similar voltage ratings may be connected to the same supply, but a deco upling capacitor should still be placed on each supply pin. note: all decoupling capacitors should be referenced to analog ground. the cdb4384 evaluation board demonstrates the optimum layout and power supply arrangements. 3.10 analog output and filtering the cs4384 does not include phase or amplitude compensa tion for an external filter. therefore, the dac system phase and amplitude resp onse will be dependent on the external analog circuitry. figure 23 shows how the full-scale analog output level specification is derived. figure 24 shows how the recommended output filtering with location for optional mute circuit aout full-scale output level= aout= 3.35 vpp 4.175 v 2.5 v 0.825 v figure 23. full-scale output figure 24. recommended output filter
ds620a1 29 cs4384 3.11 the mutec outputs the mutec1 and mutec234 pins have an auto-polarit y detect feature. the mutec output pins are high imped- ance at the time of reset. the external mute circuitry needs to be self biased into an active state in order to be muted during reset. upon release of reset, the cs4384 will detect the status of the mutec pins (high or low) and will then select that state as the polar ity to drive when the mutes become ac tive. the external-b ias voltage level that the mutec pins see at the time of release of reset mu st meet the ?mutec auto detect input high/low voltage? specs as outlined in the digital characteristics section. figure 25 shows a single example of both an active high and an active low mute drive circ uit. in these designs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold when used with the mmun2111 and mmun2211 internal bias resistances of 10 k ? . use of the mute control function is not mandatory but recommended for desi gns requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control fu nction can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. figure 25. recommended mute circuitry 3.12 recommended power-up sequence 3.12.1 hardware mode 1. hold rst low until the power supplies and configuration pi ns are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1 . in this state, the registers are reset to the default settings, filt+ will remain low, an d vq will be connected to va/2. if rst can not be held low long enough the sdinx pins should remain static low until all other clocks are stable, and if possible the rst should be toggled low again once the system is stable. 2. bring rst high. the device will remain in a low power state with fi lt+ low and will initiate the hardware power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode).
30 ds620a1 cs4384 3.12.2 software mode 1. hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1 . in this state, the registers are reset to the default settings, filt+ will remain low, and vq will be connected to va/2. 2. bring rst high. the device will remain in a low power state with filt + low for 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad- speed mode). 3. in order to reduce the chances of clicks and pops, perform a write to the cp_en bit prior to the completion of approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad-speed mode). the desired register settings can be loaded while keeping the pdn bit set to 1. set the rmp_up and rmp_dn bits to 1, then set the format and mode control bits to the desired settings. if more than the stated number of lrck cycles passes before c pen bit is written then the chip will enter hardware mode and begin to operate with the m0-m4 as the mode settings. cpen bit may be written at anytime, even after the hardware sequenc e has begun. it is advised that if the cpen bit can not be set in time then the sdinx pins should remain static low (this way no audio data can be converted incorrectly by the hardware mode settings). 4. set the pdn bit to 0. this will initiate the power-up se quence, which lasts approximately 50 s. 3.13 recommended procedure for switching operational modes for systems where the absolute minimum in clicks and pops is required, it is recommended that the mute bits are set prior to changing significant dac functions (such as changing sample rates or clock sources). the mute bits may then be released after clocks have settled and the proper modes have been set. it is required to have the device he ld in reset if the minimum high/low time specs of mclk can not be met during clock source changes. 3.14 control port interface the control port is used to load all the internal register settings in order to operate in software mode (see the ?parameter definitions? on page 48 ). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potentia l interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i2c or spi. 3.14.1 map auto increment the device has map (memory address pointer) auto increment capability enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, map will auto incremen t after each byte is wri tten, allowing block reads or writes of successive registers. 3.14.2 i2c mode in the i2c mode, data is clocked into and out of the bi-direc tional serial control data line, sda, by the serial control port clock, scl (see figure 26 for the clock to data relationship). there is no cs pin. pin ad0 en- ables the user to alter the chip address (001100[ad0][r/w ]) and should be tied to vlc or gnd as re- quired, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power- up, spi mode will be selected.
ds620a1 31 cs4384 3.14.2.1 i2c write to write to the device, follow the procedure below while adhering to the control port switching specifica- tions in section 2 . 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of the ad0 pin, and t he eighth must be 0. the eighth bit of the address byte is the r/w bit. 2. wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3. wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4. if the incr bit (see section 3.14.1 ) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i2c writes to other registers are desired, it is necessary to initiate a repeated start condition and follow the procedure det ailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus. 3.14.2.2 i2c read to read from the device, follow the procedure below while adhering to the control port switching specifica- tions. 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of the ad0 pin, and t he eighth must be 1. the eighth bit of the address byte is the r/w bit. 2. after transmitting an acknowled ge (ack), the device will then transm it the contents of the register pointed to by the map. the map register will contain the address of the last register written to the map, or the default address (see section 3.14.1 ) if an i2c read is the first operation performed on the device. 3. once the device has transmitted the contents of the register pointed to by the map, issue an ack. 4. if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. con- tinue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i2c reads from other registers are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from steps 1 and 2 from the i2c write instructions followed by step 1 of the i2c read section. if no further reads from other registers are de- sired, initiate a stop condition to the bus. sda scl 001100 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 26. control port timing, i2c mode
32 ds620a1 cs4384 3.14.3 spi ? mode in spi mode, data is clocke d into the serial control data line, cdin, by the serial control port clock, cclk (see figure 27 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. wh en the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 3.14.3.1 spi write to write to the device, follow the procedure below wh ile adhering to the control port switching specifica- tions in section 2 . 1. bring cs low. 2. the address byte on the cdin pin must then be 00110000. 3. write to the memory address pointer, map. this byte points to the register to be written. 4. write the desired data to the register pointed to by the map. 5. if the incr bit (see section 3.14.1 ) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6. if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are de- sired, bring cs high. 3.15 memory address pointer (map) 3.15.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 3.15.2 map4-0 (memor y address pointer) default = ?00000? 76543210 incr reserved reserved map4 map3 map2 map1 map0 00000000 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0011000 figure 27. control port timing, spi mode
ds620a1 33 cs4384 4. register qu ick reference addr function 7 6 5 4 3 2 1 0 01h chip revision part4 part3 part2 part1 part0 rev rev rev default 0 0 0 0 0 x x x 02h mode control cpen freeze dsd/pcm dac4_dis dac3_dis dac2_dis dac1_dis pdn default 0 0 0 0 0 0 0 1 03h pcm control dif3 dif2 dif1 dif0 reserved reserved fm1 fm0 default 0 0 0 0 0 0 1 1 04h dsd control dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd static_d sd invalid_d sd dsd_pm_ md dsd_pm_ en default 0 0 0 0 1 0 0 0 05h filter control reserved reserved reserved r eserved reserved reserved reserved filt_sel default 0 0 0 0 0 0 0 0 06h invert control inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 0 0 0 0 0 0 0 0 07h group control reserved mutec reserved p1_a=b p2_a=b p3_a=b p4_a=b snglvol default 0 0 0 0 0 0 0 0 08h ramp and mute szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 default 1 0 1 1 1 1 0 0 09h mute control mute_b4 mute_a4 mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 default 0 0 0 0 0 0 0 0 0ah mixing control pair 1 (aoutx1) reserved p1_dem1 p1_dem0 p1atapi4 p1atapi3 p1atapi2 p1atapi1 p1atapi0 default 0 0 0 0 1 0 0 1 0bh vol. control a1 a1_vol7 a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 0 0 0 0 0 0 0 0 0ch vol. control b1 b1_vol7 b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 0 0 0 0 0 0 0 0 0dh mixing control pair 2 (aoutx1) reserved p2_dem1 p2_dem0 p2atapi4 p2atapi3 p2atapi2 p2atapi1 p2atapi0 default 0 0 0 0 1 0 0 1 0eh vol. control a2 a2_vol7 a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 0 0 0 0 0 0 0 0 0fh vol. control b2 b2_vol7 b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 0 0 0 0 0 0 0 0 10h mixing control pair 3 (aoutx1) reserved p3_dem1 p3_dem0 p3atapi4 p3atapi3 p3atapi2 p3atapi1 p3atapi0 default 0 0 0 0 1 0 0 1 11h vol. control a3 a3_vol7 a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 0 0 0 0 0 0 0 0 12h vol. control b3 b3_vol7 b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 0 0 0 0 0 0 0 0 13h mixing control pair 4 (aoutx1) reserved p4_dem1 p4_dem0 p4atapi4 p4atapi3 p4atapi2 p4atapi1 p4atapi0 default 0 0 0 0 1 0 0 1
34 ds620a1 cs4384 5. register description note: all registers are read/write in i2c mode and write only in spi, unless otherwise noted. 5.1 chip revision (address 01h) 5.1.1 part number id (part) [read only] 00000- cs4384 revision id (rev) [read only] 000 - revision a0 001 - revision b0 function: this read-only register can be used to identi fy the model and revisi on number of the device. 5.2 mode control 1 (address 02h) 5.2.1 control port enable (cpen) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing the device to powe r-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the reg- isters and the pin definitions will conform to control port mode. to accomplish a clean power-up, the user should write this bit within 10 ms following the release of reset. 14h vol. control a4 a4_vol7 a4_vol6 a4_vol5 a4_vol4 a4_vol3 a4_vol2 a4_vol1 a4_vol0 default00000000 15h vol. control b4 b4_vol7 b4_vol6 b4_vol5 b4_vol4 b4_vol3 b4_vol2 b4_vol1 b4_vol0 default00000000 16h pcm clock mode reserved reserved mclkdiv reserved reserved reserved reserved reserved default00000000 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 00000 - - - 76543210 cpen freeze dsd/pcm dac4_dis dac3_dis dac2_dis dac1_dis pdn 00000001 addr function 7 6 5 4 3 2 1 0
ds620a1 35 cs4384 5.2.2 freeze controls (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to make multiple changes in t he control port registers take effect simultaneously, enable the freeze bit, make all regist er changes, then disable the freeze bit. 5.2.3 pcm/dsd selection (dsd/pcm ) default = 0 0 - pcm 1 - dsd function: this function selects dsd or pc m mode. the appropriate data a nd clocks should be present before changing modes, or else mute should be selected. 5.2.4 dac pair disable (dacx_dis) default = 0 0 - enabled 1 - disabled function: when enabled the respective dac channel pair x (aoutax and aoutbx) will rema in in a reset state. it is advised that changes to these bits be made while the power down bit is enabled to eliminate the pos- sibility of audible artifacts. 5.2.5 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur. 5.3 pcm control (address 03h) 5.3.1 digital interface format (dif) default = 0000 - format 0 (left justified, up to 24-bit data) 76543210 dif3 dif2 dif1 dif0 rese rved reserved fm1 fm0 00000011
36 ds620a1 cs4384 function: these bits select the interface format for the serial audio input. the dsd/pcm bit determines whether pcm or dsd mode is selected. the required relationship between the left/right clock, se rial clock and serial data is defined by the digital interface format and the options are detailed in figures 9 - 21 . 5.3.2 functional mode (fm) default = 11 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - auto speed mode detect (3 2 khz to 200 khz sample rates) function: selects the required range of input sample rates or auto speed mode. 5.4 dsd control (address 04h) 5.4.1 dsd mode digital interface format (dsd_dif) default = 000 - format 0 (64x oversampled dsd data with a 4x mclk to dsd data rate) function: the relationship between the oversampling ratio of t he dsd audio data and the required master clock to dsd data rate is defined by the digital interface format pins. dif3 dif2 dif1 dif0 description format figure 0000 left justified, up to 24-bit data 0 9 0001 i 2 s, up to 24-bit data 1 10 0010 right justified, 16-bit data 2 11 0011 right justified, 24-bit data 3 12 0100 right justified, 20-bit data 4 13 0101 right justified, 18-bit data 5 14 1000 one-line mode 1, 24-bit data +sdin4 8 15 1001 one-line mode 2, 20-bit data +sdin4 9 17 1010 one-line mode 3, 24-bit 6-channel 10 18 1011 one-line mode 4, 20-bit 6-channel 11 20 1100 tdm 12 21 xxxx all other combinations are reserved table 7. digital interface formats - pcm mode 765 4 3 2 1 0 dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd static_dsd invalid_dsd dsd_pm_md dsd_pm_en 000 0 1 1 0 0
ds620a1 37 cs4384 the dsd/pcm bit determines whether pcm or dsd mode is selected. 5.4.2 direct dsd c onversion (dir_dsd) function: when set to 0 (default), dsd input data is sent to the dsd processor for filterin g and volume control func- tions. when set to 1, dsd input data is sent directly to the switched capacitor dacs for a pure dsd conversion. in this mode the full scale dsd and pcm levels will not be matched (see section 2 ), the dynamic range performance may be reduced, the volume control is inac tive, and the 50 khz low pass filter is not available (see section 2 for filter specifications). 5.4.3 static dsd detect (static_dsd) function: when set to 1 (default), the dsd processor checks fo r 28 consecutive zeroes or ones and, if detected, sends a mute signal to the dacs. the mutec pins will eventually go active according to the damute register. when set to 0, this function is disabled. 5.4.4 invalid dsd de tect (invalid_dsd) function: when set to 1, the dsd processor checks for greater t han 24 out of 28 bits of the same value and, if de- tected, will attenu ate the data sent to the dacs. the mutec pins go active according to the damute register. when set to 0 (default), this function is disabled. 5.4.5 dsd phase modulation m ode select (dsd_pm_mode) function: when set to 0 (default), the 128fs (bcka) clock should be input to dsd_sclk for phase modulation mode. (see figure 20 on page 26 .) when set to 1, the 64fs (bckd) clock should be input to dsd_sclk for phase modulation mode. dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate. 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate. 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate. 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate. table 8. digital interface formats - dsd mode
38 ds620a1 cs4384 5.4.6 dsd phase modulation mode enable (dsd_pm_en) function: when set to 1, dsd phase modulation input mode is enabled and the dsd_pm_mode bit should be set accordingly. when set to 0 (default), this func tion is disabled (dsd normal mode). 5.5 filter control (address 05h) 5.5.1 interpolation filter select (filt_sel) function: when set to 0 (default), the interpolation filter has a fast roll off. when set to 1, the interpolation filter has a slow roll off. the specifications for each filter can be found in the analog characteri stics table, and response plots can be found in figures 26 to 49 . 5.6 invert control (address 06h) 5.6.1 invert signal polarity (inv_xx) function: when set to 1, this bit inverts the signal polarity of channel xx. when set to 0 (default), this function is disabled. 5.7 group contro l (address 07h) 5.7.1 mutec pin control (mutec) default = 0 0 - two mute control signals 1 - single mute control signal on mutec1 function: selects how the internal mute signals are routed to the mutec1 and mutec234 pins. when set to ?0?, a logical and of dac pair 1 mute control signals are output on mutec1 and a logical and of the mute control signals of dac pairs 2, 3, and 4 are output on mutec234. when set to ?1?, a logical and of all dac pair mute control signals is ou tput on the mutec1 pin, mutec234 will remain stat ic. for more in- formation on the use of the mute control func tion see the mutec1 and mutec234 pins in section 3.11 . 76543210 reserved reserved reserved reserved reserved reserved reserved filt_sel 00000000 76543210 inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 reserved mutec reserved p1_a=b p2_a=b p3_a=b p4_a=b snglvol 00000000
ds620a1 39 cs4384 5.7.2 channel a volume = ch annel b volume (px_a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are independ ently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aoutax and aoutbx are deter- mined by the a channel attenuation and volume control bytes (per a-b pair), and the b channel bytes are ignored when this function is enabled. 5.7.3 single volume control (snglvol) default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independent ly controlled by their re spective volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel volume control byte, and the other volume control byte s are ignored when this function is enabled. 5.8 ramp and mute (address 08h) 5.8.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross zero cross enable dict ates that signal level cha nges, either by attenuation changes or muting, will occur on a signal zero crossing to mini mize audible artifacts. the reques ted level change will occur after a tim- eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. 76543210 szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 10111100
40 ds620a1 cs4384 soft ramp on zero crossing soft ramp and zero cross enable di ctates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps an d be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period betwee n 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 5.8.2 soft volume ramp-u p after error (rmp_up) function: an un-mute will be performed after ex ecuting an lrck/mclk ratio chan ge or error, and after changing the functional mode. when set to 1 (default), this un-mute is effected, si milar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate un-mute is performed in these instances. note: for best results, it is recomme nded that this feature be used in conjunction with the rmp_dn bit. 5.8.3 soft ramp-down before fi lter mode cha nge (rmp_dn) function: if either the filt_sel or dem bi ts are changed the dac will stop co nversion for a period of time to change its filter values. this bit selects how the data is effected prior to and af ter the change of the filter values. when set to 1 (default), a mute will be performed pr ior to executing a filter mode change an d an un-mute will be performed after executing the filter mode change. this mute a nd un-mute are effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 5.8.4 pcm auto-mute (pamute) function: when set to 1 (default) the digital-to-analog converter output w ill mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-st atic data will release the mute. de- tection and muting is d one independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. when set to 0 this function is disabled. 5.8.5 dsd auto-mute (damute) function: when set to 1 (default) th e digital-to-analog converter output will mu te following the reception of 256 re- peated 8-bit dsd mute patterns (as defined in the sacd specification). a single bit not fitting the repeated mute pattern (m entioned above) will releas e the mute. detection and muting is done indepen dently for each channel. t he quiescent voltage on the output will be retained and the mute control pin will go ac tive during the mute period.
ds620a1 41 cs4384 5.8.6 mute polarity and detect (mutep1:0) default = 00 00 - auto polarity detect, selected from mutec1 pin 01 - reserved 10 - active low mute polarity 11 - active high mute polarity function: auto mute polarity detect (00) see section 3.11 on page 29 for the description. active low mute polarity (10) when rst is low the outputs are high impedance and will need to be bias ed active. once reset has been released and after this bit is set, the mutec output pins will be active low polarity. active high mute polarity (11) at reset time the outputs are high impedance and will need to be biased active. once reset has been re- leased and after this bit is set, the mu tec output pins will be active high polarity. 5.9 mute control (address 09h) 5.9.1 mute (mute_xx) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter out put will mute when enabled. the qu iescent voltage on the output will be retained. the muting function is affected, similarl y to attenuation changes, by the soft and zero cross bits. the mute pins will go active during the mute peri od according to the mutec bit. 5.10 mixing control (addre ss 0ah, 0dh, 10h, 13h) 5.10.1 de-emphasis control (px_dem1:0) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: 76543210 mute_b4 mute_a4 mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 00000000 76543210 reserved px_dem1 px_dem0 pxatapi4 pxatapi3 pxatapi2 pxatapi1 pxatapi0 00001001
42 ds620a1 cs4384 selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. ( figure 20 on page 26 ) de-emphasis is only availa ble in single-speed mode. 5.11 atapi channel mixi ng and muting (atapi) default = 01001 - aoutax=al, aoutbx=br (stereo) function: the cs4384 implements the channel mixing functions of the atapi cd-rom sp ecification. the atapi functions are applied per a-b pair. refer to table 9 and figure 21 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 9. atapi decode
ds620a1 43 cs4384 5.12 volume control (address 0bh, 0ch, 0eh, 0fh, 11h, 12h, 14h, 15h) these eight registers provide individual volume and mute control for each of the eight channels. the values for ?xx? in the bit fields above are as follows: register address 0bh - xx = a1 register address 0ch - xx = b1 register address 0eh - xx = a2 register address 0fh - xx = b2 register address 11h - xx = a3 register address 12h - xx = b3 register address 14h - xx = a4 register address 15h - xx = b4 5.12.1 digital volume control (xx_vol7:0) default = 00h (0 db) function: the digital volume control registers allow independent control of the signal le vels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 10 . the volume changes are imple- mented as dictated by the soft and zero cross bits in the power and muting control register. note that the values in the volu me setting column in table 10 are approximate. the actual attenuation is determined by taking the decimal value of the volu me register and multiplying by 6.02/12. 5.13 pcm clock mode (address 16h) 5.13.1 master clock divide by 2 enable (mclkdiv) function: when set to 1, the mclkdiv bit enables a circuit wh ich divides the externally applied mclk signal by 2 prior to all other in ternal circuitry. when set to 0 (default), mclk is unchanged. 76543210 xx_vol7 xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 -127.5 db table 10. example digital volume settings 76543210 reserved reserved mclkdiv reserved r eserved reserved reserved reserved 00000000
44 ds620a1 cs4384 6. filter resp onse plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 28. single-speed (fast) stopband rejectio n figure 29. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 30. single-speed (fast) transition band (detail) figure 31. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 32. single-speed (slow) stopband rejection figure 33. sing le-speed (slow) transition band
ds620a1 45 cs4384 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 34. single-speed (slow) transition band (d etail) figure 35. single-s peed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 36. double-speed (fast) stopband rejectio n figure 37. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 38. double-speed (fast) transition band (detail) figure 39. double-speed (fast) passband ripple
46 ds620a1 cs4384 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 40. double-speed (slow) stopband rejection figure 41. doub le-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 42. double-speed (slow) transition band (d etail) figure 43. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 44. quad-speed (fast) stopband rejection figure 45. quad-speed (fast) transition band
ds620a1 47 cs4384 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 46. quad-speed (fast) transition band (detail) figure 47. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 48. quad-speed (slow) stopband rejectio n figure 49. quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 50. quad-speed (slow) transition band (det ail) figure 51. quad-speed (slow) passband ripple
48 ds620a1 cs4384 7. references 1. how to achieve optimum performance fr om delta-sigma a/d & d/a converters, by steven harris. paper presented at the 93rd convention of th e audio engineering society, october 1992. 2. cdb4364 datasheet 3. design notes for a 2-pole f ilter with diffe rential input, by steven green. cirrus logic application note an48 4. the i2c -bus specification: version 2.0, philips semiconductors, december 1998. http://www.semiconductors.philips.com 5. an282 ?the 2-channel serial audio interface: a tutorial? 8. parameter definitions total harmonic distor tion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-no ise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion comp onents are below the noise level and do not affect the measurement. this measurement technique has been a ccepted by the audio engineering society, aes17- 1991, and the electronic industries association of ja pan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each c hannel at the converter's output with all zeros to the input under test and a full-sca le signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c.
ds620a1 49 cs4384 9. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
50 ds620a1 cs4384 10.ordering information 11.revision history release date changes a1 august 2005 initial release product description package pb-free grade temp range container order # cs4384 114 db, 192 khz 8- channel d/a con- verter 48-pin lqfp yes commercial -10 to +70 c tray cs4384-cqz tape & reel cs4384-cqzr automotive -40 to +85 c tray cs4384-dqz tape & reel CS4384-DQZR cdb4384 cs4384 evaluation board - - - - cdb4384 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant informati on to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage ("critical applications"). ci rrus products are not designed, authorized or warranted for use in aircraft systems, milita ry applications, product s surgically implanted into the body, automotive safety or security devices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer's risk and cirrus disclaims a nd makes no warranty, express, statutory or implied, includ- ing the implied warranties of merchantability and fitness fo r particular purpose, with regard to any cirrus product that is used in such a manner. if the custo mer or customer's custo mer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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